DDR4 stopped its development at 16 gigabit chips, which allowed for 32GB UDIMM/SODIMM and 64GB RDIMM modules. DDR5 can use 64 gigabit modules. This will allow you to have bars up to 2TB in the future. The "household" sector will most likely be able to grow to 128GB per module. But since 16 gigabit chips are currently being used in production, 32GB per module is our lot.
Compared to DDR4, the bank groups of DDR5 memory have increased from 4 to 8, and the total number of banks has increased from 16 to 32. The number of bank groups has been doubled, which helps to increase the amount of data transferred, thereby optimizing the overall timing parameters. Increasing the number of banks from 16 to 32 allows you to open more pages in a row. DDR5 also has a single bank refresh feature (SBRF) that allows one bank per group to be refreshed instead of all banks.
The specification specifies data transfer rates from DDR5-3200 to DDR5-6400. DDR4 at one time started with a minimum of 1600, DDR5 manufacturers started with a mark of 4800.
The number of contacts on the module remained the same, 288, but the pinout changed. The key on the module has been moved. Now, to install a DDR5 bar in a DDR4 slot, you need character and strong hands.
DDR5 memory is designed with a new channel architecture that provides two sets of fully independent 32-bit subchannels (DDR4 has one 64-bit channel). Dual bandwidth mode increases overall performance, reduces access latency, and increases link efficiency.
Server DDR5 RDIMM memory has two 40-bit subchannels, adding 8 bits to the existing 32 bits of each channel to support the ECC error detection and correction mechanism. The design of the RCD (Registering Clock Driver) allows you to further reduce the load on the central processor, strengthen the integrity of the signal and reduce interference.
DDR5 is more energy efficient. Operating voltage reduced from 1.2V DDR4 to 1.1V. These are standard values. As we remember, going beyond the specification, it was possible to reach DDR4-5000 at 1.6V. Most likely, we will get DDR5-6800 with a 1.35V power supply.
Radical changes have taken place in power regulation. Instead of the traditional motherboard control method, DDR5 memory is equipped with a power management IC (PMIC), which can more effectively manage system load and improve power conversion efficiency. This allows memory manufacturers to flexibly respond to customer requests by including additional functionality in the PMIC to improve reliability, temperature monitoring - improving overall performance in both full-bandwidth and low-power states.
On the one hand, such a solution potentially simplifies, therefore, makes motherboards cheaper (not noticed), on the other hand, it complicates and makes memory modules more expensive (noticed). Now the module manufacturers are not only depending on the memory chip manufacturers, but also on some Integrated Device Technology, Inc that produces PMIC.
There are currently two PMIC specifications. DDR5 UDIMMs and SODIMMs that use 5V PMICs; for server applications, DDR5 RDIMM server memory uses 12V PMIC.
A 14-month study of Facebook's entire server fleet found that the majority of memory errors were related to the memory controller and memory channel. At the same time, the study showed that the increase in the density of memory chips, the increase in their number per module and the increase in bus width cause an increase in the number of errors from generation to generation of memory. Contrary to popular belief, memory errors are not always isolated events and can strike a server (if not handled properly) creating a denial of service attack of sorts.
On-die ECC (ODECC) is another important feature of the DDR5 specification. This technology is designed to combat the increase in the number of errors associated with the increase in the density of the DDR5 layout. Unfortunately, the protection is limited to the memory arrays inside the chips - as soon as the data goes outside the DIMM, it becomes independent. Embedded ECC does not provide any protection for data in transit, so embedded ECC is not a correct full implementation of ECC.
It should not be forgotten that the built-in ECC requires additional capacity to store parity, which is another reason for the increase in the cost of DDR5 (in addition to the PMIC). Embedded ECC will not replace standard ECC, but both options will be used in server and enterprise environments.
Briefly, about the motives and main milestones of the transition to DDR5.
Multicore CPU
The more cores a processor has, the less available memory bandwidth per core. Due to fundamental changes in the DRAM architecture, the effective bandwidth of DDR5 is more than twice that of DDR4 – which is important for memory-intensive multi-threaded workloads
Feeding and managing it
The standard operating voltage for DDR5 is 1.1V compared to 1.2V for DDR4. Even without overclocking, DDR5 leaves more room for performance management. The power management integrated circuit (PMIC) chip is located on the DDR5 DIMM itself. For DDR4, it was placed on the motherboard.
Doubling
The DDR5 standard offers twice the number of memory bank groups, twice the packet length, and two independent 32-bit channels on non-ECC memory modules. DDR4 had one 64-bit channel.
On-die ECC
The error correction built into the module does not replace, but complements the standard ECC checks - which are still performed by the processor with the support of the motherboard. The density of the DDR5 layout requires the expansion of data protection mechanisms in the memory.
Content creators, mathematical modeling practitioners, engineers who work with large volumes of data, multitasking users - all use processors with a large number of cores. DDR5 is better suited for multi-threading than DDR4. With the increasing popularity and decreasing prices of DDR5 modules, there are fewer and fewer reasons to hold back on the latest generation technology.
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