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DDR4 stopped in its development at 16-gigabit chips, which allowed for the creation of 32GB UDIMM/SODIMM and 64GB RDIMM modules. DDR5 can use 64-gigabit modules. This will allow for up to 2TB in the future. The "consumer" sector will most likely be able to grow to 128GB per module. But since 16-gigabit chips are currently used in production, 32GB per module is our lot.
Compared to DDR4, DDR5 memory bank groups have been increased from 4 to 8, and the total number of banks has been increased from 16 to 32. The number of bank groups has been doubled, which helps to increase the amount of data transferred, thereby optimizing the overall timing parameters. The increase in the number of banks from 16 to 32 allows more pages to be opened in a row. DDR5 also has a Single Bank Refresh Function (SBRF), which allows one bank per group to be refreshed instead of all banks.
The specification defines data transfer speeds from DDR5-3200 to DDR5-6400. DDR4 at one time started with a minimum of 1600, DDR5 manufacturers started at 4800.
The number of contacts on the module remained the same, 288, but the pinout changed. The key on the module has been moved. Now, to install a DDR5 bar in a DDR4 slot, you need to have character and strong hands.
DDR5 memory is designed with a new channel architecture that provides two sets of fully independent 32-bit subchannels (DDR4 has a single 64-bit channel). Dual-bandwidth mode increases overall performance, reduces access latency, and improves channel efficiency.
The DDR5 RDIMM server memory has two 40-bit subchannels, adding 8 bits to the existing 32 bits per channel to support ECC error detection and correction. The RCD (Registering Clock Driver) design further reduces CPU load, enhances signal integrity, and reduces interference.
DDR5 has higher energy efficiency. The operating voltage has been reduced from 1.2V DDR4 to 1.1V. These are standard values. As we remember, going beyond the specification, it was possible to achieve DDR4-5000 at 1.6V. Most likely, we will get DDR5-6800 at 1.35V power supply.
Power regulation has undergone a radical change. Instead of the traditional motherboard-based control method, DDR5 memory is equipped with a power management IC (PMIC) that can more effectively manage system loads and improve power conversion efficiency. This allows memory manufacturers to flexibly respond to customer requests by including additional functionality in the PMIC to improve reliability, temperature monitoring - improving overall power performance in both full-bandwidth and reduced-power states.
On the one hand, such a solution potentially simplifies, therefore, makes motherboards cheaper (not noticed), on the other hand, it complicates and makes memory modules more expensive (noticed). Now module manufacturers are not only dependent on memory chip manufacturers, but also on some Integrated Device Technology, Inc, which produces PMICs.
There are currently two PMIC specifications. DDR5 UDIMM and SODIMM, which use 5V PMICs; for server applications, DDR5 RDIMM server memory uses 12V PMICs.
A 14-month study of Facebook's entire server fleet found that most memory errors were related to the memory controller and memory channel. However, the study found that increasing memory chip density, increasing the number of chips per module, and increasing bus widths are causing the number of errors to increase from generation to generation of memory. Contrary to popular belief, memory errors are not always isolated events and can hit a server (if not handled properly), creating a kind of denial-of-service attack.
On-die ECC (ODECC) is another important feature of the DDR5 specification. This technology is designed to combat the increasing number of errors associated with the increase in DDR5 layout density. Unfortunately, the protection is limited to the memory arrays inside the chips - once the data leaves the DIMM, it becomes independent. Embedded ECC does not provide any protection for data in transit, so embedded ECC is not a proper full implementation of ECC.
It should be noted that embedded ECC requires additional parity storage capacity, which is another reason for the increased cost of DDR5 (in addition to the PMIC). Embedded ECC will not replace standard ECC, but both options will be used in server and enterprise environments.
Briefly, about the motives and main milestones of the transition to DDR5.
Multi-core CPU
The more cores a processor has, the less memory bandwidth is available per core. Thanks to fundamental changes in DRAM architecture, DDR5 has more than twice the effective bandwidth of DDR4 – important for memory-intensive multithreaded workloads
Nutrition and its management
The standard operating voltage for DDR5 is 1.1V compared to 1.2V for DDR4. Even without overclocking, DDR5 leaves more room for efficiency management. The power management integrated circuit (PMIC) chip is located on the DDR5 DIMM itself. For DDR4, it was located on the motherboard.
Doubling
The DDR5 standard offers double the number of memory bank groups, double the packet length, and two independent 32-bit channels on non-ECC memory modules. DDR4 had a single 64-bit channel.
On-die ECC
The module's built-in error correction does not replace, but complements, standard ECC checks – which are still performed by the processor with motherboard support. The density of DDR5 layout requires expanded data protection mechanisms in memory.
Content creators, mathematical modelers, data scientists, and multitaskers all rely on processors with more cores. DDR5 is better suited for multithreading than DDR4. With DDR5 becoming more popular and coming down in price, there is less reason to hold back on the latest generation technology.
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